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Flattened butterfly processor interconnect network
Flattened butterfly processor interconnect network
A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.
Original Text (This is the original text for your reference.)
A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.
Inventor: Dennis C. Abts,John Kim,William J. Dally
Application number: 12195190
Publication number: 08285789
Filing date: 2008-08-19
Publication date: 2012-10-08
Type of Patent: B2
Source: IKCEST
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