Abstracts:This paper introduces a novel additivemanufacturing technique to obtain high-resolution selective-ink-deposition on complex 3-D objects, packages, and modules for 5G applications. The technique consists of embossing the desired pattern directly on the 3-D printed dielectric surface and then applying ink with a suitable tool. This approach is tested in combination with stereolithography 3-D printing technology to obtain selectively metallized 3-D circuits. In particular, the “clear” resin from FormLab is utilized for the 3-D printed dielectric, while the metallization is performed with silver nanoparticle ink from Suntronic. As a preliminary study, test samples containing lines with different widths are manufactured, demonstrating a pitch down to 135 μm and satisfactory sheet resistance of 0.011 Q/sq. (the electromagnetic characterization of the dielectric resin is reported in the Appendix). Then, two broadband multiport RF structures are developed to show the versatility of the proposed technology. First, an ultrawideband 3-D crossover, operating in the range 100 MHz-5 GHz, is conceived to test the suitability of the proposed technology to perform selective metallization on curved semi-enclosed areas. Then, the technology is applied to a multiple-input-multiple-output (MIMO) antenna system, based on four proximity-fed annular slot antennas, arranged on the lateral sides of a cube and decoupled by introducing a cross-shaped structure in the interior of the cube. This circuit offers a broad range of metallization challenges, as it features embossed and engraved parts, high-resolution patterns (line widths down to 0.7 mm) and sharp edges. Each slot radiates unidirectionally with the same polarization and uses the cube and its internal cross-shaped structure as a resonant cavity. The antenna system is designed to operate in the band 3.4-3.8 GHz, which is one of the sub-6-GHz 5G bands in Europe, and it is thought - or hotspot and access-point applications. The final antenna topology is composed of only two blocks, weighs 21.29 g, and occupies a volume of 44.4 × 45.8 × 45.8 mm³, featuring an envelope correlation coefficient (ECC) lower than 0.005 and a total active reflection coefficient (TARC) lower than -6 dB in all the bands of interests.

Abstracts:This paper presents the latest advances in photolithography technologies to enable scaling of package redistribution layer (RDL) toward critical dimensions (CD) of 1 μm and below. High-bandwidth memory channels require not only fine pitch but also low-trace-delay RDL. High-aspect-ratio (AR) traces enable lower delays, and the photolithographic advances to achieve such traces are demonstrated on panel-based glass substrates for packages with low cost, high input/output (I/O) density, high bandwidth, and large body size. CD of 0.9-μm line and space with an AR of 5.5 was successfully demonstrated using a low-numerical aperture (NA = 0.16) 1x i-line projection stepper tool with a novel chemically amplified plating photoresist. The 1-μm lithography technology is a must for high-density RDL to enable 2.5-D interposer and embedded fan-out package substrates. These architectures can achieve I/O densities of 500 IOs/mm/layer. The resistance of the trace with an AR of 5 is five times lower than a trace with an AR of 1. This technological advance will greatly reduce the signal propagation loss and increase the data rate of the RDL traces. The combination of high density and high data rate will greatly increase the system interconnect bandwidth. Furthermore, low-NA stepper with a large exposure area will enable the fabrication of large-body-size interposers at low cost. This paper analyzes the relationship between trace width resolution (w), depth of focus, and materials to conclude that it is feasible to fill the gap between semiconductor backend-of-line and package substrate RDL technologies. The final section discusses the issues in process development of lithography for multilayer fine-line RDLs.

Abstracts:The integration of small wafer-based devices into flexible polymeric systems allows the fabrication of smart systems. Such systems are of high interest and are being developed in different fields. Active implants for biomedical applications promise new insights and therapy possibilities including the novel field of electroceuticals, which focuses on the treatment of systemic diseases by neuromodulation. For the fabrication of a new active flexible microelectrode array, we developed a process that allows the embedding of an array of small CMOS dies into a polymer foil. The process includes a transfer printing process based on adhesion, transferring the desired of the separated dies from UV-curable dicing tape to a substrate coated with sugar solution. The transfer printing process has shown to be highly reliable and selective, yielding a transfer success rate of 100&#x0025; in most cases. The relative position of the transferred dies is conserved to less than <inline-formula> <tex-math notation="LaTeX">$15~mu text{m}$ </tex-math></inline-formula> lateral displacement. To evaluate the process, the pull-off strength of the employed silicone stamps was measured. For stamps made of soft silicone, a pulling strength up to 83 kPa was obtained. In addition to this, a process for the embedding of the dies into a flexible foil system is presented. Using polydimethylsiloxane, the topography due to the dies&#x2019; height is reduced from more than <inline-formula> <tex-math notation="LaTeX">$200~mu text{m}$ </tex-math></inline-formula> to approximately <inline-formula> <tex-math notation="LaTeX">$10~mu text{m}$ </tex-math></inline-formula>, enabling the use of standard microelectromechanical fabrication processes on top.

Abstracts:This paper presents waveguide interconnects implemented in an embedded wafer level ball grid array (eWLB) packaging technology. The interconnects operate at D-band (110-170 GHz), hence are enabling the realization and commercialization of high-data-rate systems. The interconnects rely on implementing radiating structures on the technology's redistribution layers instead of using conventional ball grid arrays for the transmission of the RF signal to/from the package. The interconnects interface with standard WR-6.5 waveguides. Moreover, they do not require any galvanic contacts with the waveguide. The interconnects achieve a measured insertion loss of 2.8 dB over a bandwidth of 33%. The adopted eWLB packaging technology is suitable for low-cost high-volume production and allows heterogeneous integration with other technologies. This paper proposes cost-effective high-performance interconnects for THz integration, thus addressing one of the main challenges facing systems operating beyond 100 GHz.

Abstracts:In this paper, warpage of fan-out wafer-level packaging (FOWLP) throughout the manufacturing process is investigated to minimize the warpage. FOWLP technology has the advantages of low cost, small form factor, efficient electrical performance, and increased input-output counts. The main benefit of fan-out packaging is that it utilizes the redistribution layer to interconnect the die and solder joints instead of using the substrate. However, warpage control is still a critical issue in the wafer molding process. Warpage is induced by the coefficient of thermal expansion mismatch between the die and the molding compound. Throughout the manufacturing process, the warpage of each step was recorded by utilizing the continuity simulation. The debonding process, grinding process, and annealing process at room temperature were analyzed via the simulation results and the experimental results. To simulate the wafer molding process in a continuous manner, the element birth and death technique was employed using finite-element modeling. This method can be used to reactive and deactivate elements when the material is added to or removed from the system. The results of the measurement and simulation were highly similar, with a difference of less than 10%. However, the results differed considerably when the wafer thickness was small. The results revealed a gap between the experimental testing and simulation modeling. Because of the wafer stiffness, the wafer is too thin to support the gravity force in the experimental testing process. Therefore, it is important to determine the calibration factor to decrease the gap between experimental testing and simulation modeling. In addition, it is crucial to determine the key factor controlling the warpage behavior and to minimize the warpage by evaluating the die arrangement and the die size in this paper. Overall, the simulation modeling represents a feasible approach for predicting the warpage during the manufacturing process.

Abstracts:Accurate peeling off and transferring of microchips play a critical role in LED die sorting technology. Generally, sorting efficiency of more than 36 KUPH, and an alignment deviation less than 1 mil (25.4 &#x03BC;m) is required. High precision position control and cooperation of multifactors should be implemented precisely. Among all the factors, the film deformation is an important one. As the sorting proceeds, dies are peeled off from substrates one by one, and the adhesive substrate is penetrated through a hole each time. As the number of stripped chips increases, viscoelastic deformation of tape surface takes place and tiny position shift of die adhered on tape arises. This shift may cause a negative impact on the peeling process. In this paper, linear viscoelastic deformation impact is tested with well-designed experiments. To evaluate the effect of tape deformation accurately for sorting the performance, stochastic Petri net model of the transferring system with dual-independent arms is formulated to analyze the influence of factors. On this basis, strategy on coordinating motion control and scheduling is proposed, rational velocity section is planned, and the active position compensation of supply platform is set, so that the die can be peeled off correctly and efficiently. Finally, to improve sorting performance, methods on active compensation of aligning platform are proposed and proven effective by an experimental validation.

Abstracts:Light-emitting diodes (LEDs) are emerging lighting sources. However, it is still difficult to obtain good optical consistency of LEDs from the same batch due to phosphor sedimentation. In this paper, we introduce the centrifugation method to enhance the optical consistency of LEDs. The phosphor gradient concentration model is proposed to simulate the changes of phosphor concentration in different centrifugation time and acceleration. Moreover, the effect of these parameters on the optical performance of LEDs is discussed. The simulation results reveal that increasing centrifugal acceleration and time can enhance the optical consistency of LEDs by changing the phosphor distributions. It is suggested that the centrifugation parameters with 20 times gravitational acceleration and 6 min centrifugation time can ensure high optical consistency for LEDs, which can be taken as a reference to balance optical performance and consistency. Experimental results validate that the proposed method is beneficial to improve the optical consistency, including luminous flux and color coordinates, compared to LEDs without centrifugation.

Abstracts:Stochastic spectral methods have achieved a great success in the uncertainty quantification of many engineering problems, including variation-aware electronic and photonic design automation. State-of-the-art techniques employ generalized polynomial-chaos expansions and assume that all random parameters are independent or Gaussian correlated. This assumption is rarely true in real applications. How to handle non-Gaussian correlated random parameters is a long-standing and fundamental challenge: It is not clear how to choose basis functions and to perform a projection step in a correlated uncertain parameter space. This paper first presents a new set of basis functions to well capture the impact of non-Gaussian correlated parameters and then proposes an automatic and optimization-based quadrature method to perform projection-based stochastic collocation with a few simulation samples in the correlated parameter space. We further provide some theoretical proofs for the complexity and error bound of our proposed method. The numerical experiments on several synthetic, electronic, and photonic integrated circuit examples show the nearly exponential convergence rate of our approach and its significant (700&#x00D7;-6000&#x00D7;) speedup than Monte Carlo. Many other open problems with non-Gaussian correlated uncertainties can be further solved based on this paper.

Abstracts:Arc chutes comprising ferromagnetic splitter plates are common in SF6-insulated medium-voltage switchgears. By splitting and cooling the electric arc, they help to interrupt moderate currents such as the rated current in load break switches or the transfer current in switch-fuse combinations. Between the splitter plates of such an arc chute, the motion of the arc depends on the balance of the attracting magnetic forces from the ferromagnetic plates, the repelling forces between two arc columns at the two sides of a plate, and the viscous forces from the insulating gas. We simulated this motion by calculating the magnetic forces acting on the arc columns after splitting by means of 2-D and 3-D electromagnetic finite-element analyses and by taking the viscous force as drag force into account. This paper describes this calculation method and compares the simulation results with those of laboratory tests.

Abstracts:A novel ultrawideband and miniaturized common-mode filter (CMF) is proposed for suppressing the CM noise based on the dual vertical coupling paths. In the proposed CMF, a modified quarter-wavelength transmission line resonator and a modified half-wavelength transmission line resonator are utilized to introduce three CM transmission zeros. Moreover, another CM transmission zero is produced by the dual vertical path coupling. An ultrawide CM stopband is achieved by the four CM transmission zeros. Subsequently, equivalent circuit models have been established to give physical insight into the CMF operating mechanism, and the design procedures are also provided. By using the low-temperature cofired ceramic technology, a surface-mounted device prototype is fabricated and measured. The measured results show that the CM noise can be suppressed over 10 dB from 2.45 to 9.85 GHz with 120.3% fractional bandwidth. Meanwhile, the low insertion loss and the relatively constant group delay for differential mode ensure that the proposed CMF can maintain the signal integrity of differential signals below 10 GHz.