Abstracts:Wiener model belongs to a broad class of non-linear model structures called the block-oriented models. Various chemical, biological and electrical processes can be represented as a Wiener structure. There are vast numbers of approaches to identify the Wiener model; however, most of them are only theoretically sound. Therefore, there is a need for developing an industrial grade, simple identification scheme. The present research work attempts to explore the possibility of identifying Wiener models using relay feedback identification technique, which has been applied efficiently but limited mostly to linear structures. Here, the authors consider not all but wider probable cases of the linear subsystem, which include real roots, complex conjugate roots, first-order, integrating second-order and repeated roots. The proposed method is simple and requires less prior knowledge about the system. The technique being somehow general can be applied effectively to linear and unstable systems as well. Various simulation examples are used to demonstrate the efficacy of the proposed identification scheme.

Abstracts:Time-based successive approximation register (SAR) analogue-to-digital converters (ADCs) are gaining attraction in ultra-low voltage circuit design. Such ADCs typically use multi-stage voltage controlled delay lines (VCDLs) to perform voltage to time conversion in order to mitigate limited headroom of voltage signals. Although multi-stage VCDLs are used, only the outputs of the final VCDL stages are compared during bit trials. This work demonstrates that additional bit information can be extracted by scavenging timing information revealed at VCDL intermediate stages. The additional bit information can be used to accelerate the ADC conversion process or improve signal-to-noise distortion ratio (SNDR). To cope with uncertainties associated with signals from VCDL intermediate stages, an uncertainty-tolerant SAR procedure is developed. Also, this work presents techniques for adaptively selecting which intermediate stage signals to be tapped along the conversion process. The proposed techniques are applied in the design of a 0.4 V 9-bit SAR ADC in a 130 nm CMOS technology. Silicon measurement results show that with the additional information extracted from VCDL intermediate stages the conversion for the vast majority of ADC inputs can be completed in 7 or 8 clock cycles. Measurement results also demonstrate the potentials of using the intermediate stage signals to improve ADC SNDR.

Abstracts:This research work presents a novel approach to design efficient power-of-two multipliers on modern field-programmable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.

Abstracts:Security and privacy of the Internet of Things (IoT) systems are critical challenges in many data-sensitive applications. The IoT systems are constrained in terms of execution time, flexibility and computational resources. In recent years, many encryption algorithms have been proposed to provide the security of IoT communication. In this study, flexible and high-throughput hardware structures of the PRESENT, SIMON, and LED lightweight block ciphers are presented for IoT applications. The proposed flexible structures can perform various configurations of these block ciphers to support variable key sizes. For example, the PRESENT, SIMON, and LED ciphers support key sizes (80, 128 bits), (96, 144, 128, 192, and 256 bits), and (64, 128 bits), respectively. Therefore, these architectures provide versatile implementations that enable adaptive security level using a variable key size. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. In the PRESENT and LED ciphers, the S-boxes are implemented based on area-optimised logic circuits. The implementation results of proposed flexible architectures are achieved in 180 nm CMOS technology. Area, throughput and throughput/area of the proposed structures have improved compared to other related works.

Abstracts:Compressors are fundamental components in multi-operand addition and multiplication hardware. The present study aims to propose several high-speed hybrid designs of 4:2 compressors which are implemented based on multi-threshold logic and transmission gate multiplexers, at low supply voltages. In order to implement these circuits, carbon nanotube field-effect transistors (CNFETs) are utilised. The division of the entire input capacitor network in the third proposed design causes the entire structure operates faster and consumes less power. All designs were simulated with Synopsys HSPICE and $32, {rm nm}$32 nm CNFET technology in different conditions. Simulation results demonstrate the superiority of the third proposed design with regard to different load and frequency conditions. In addition, it becomes less sensitive to process, voltage and temperature variations compared to other similar capacitive threshold logic circuits. The results indicate the third proposed design outperforms the best reference design in terms of delay and power-delay product by 34 and 25%, respectively. Furthermore, the performance of each design was evaluated in a 8 × 8-bit binary multiplier as a uniform test bench, which confirmed the above results on isolated single 4:2 compressors.

Abstracts:Rechargeable batteries are critical components in many electrical systems nowadays. One has to ensure reliable diagnosis and assessment of the installed batteries for smooth and safe operations. Assessment of the remaining capacity of a battery is crucial diagnostic information. A battery management system (BMS) needs to reliably report the ability of the battery to supply power or the lack thereof. If the BMS fails to do so at an early stage, this may compromise the health of the entire electric system. When a battery nears a region where the battery state-of-charge (SOC) is low, there is a risk of an abrupt drop in the terminal voltage. An early detection of such a region is crucial; otherwise, the BMS may not have enough time to react. To address this issue, our work provides a novel supervised learning approach towards an early detection of Li-ion battery terminal voltage collapse. No knowledge of initial SOC or battery model parameters is required. This is particularly important as batteries lose their capacity to store charge over time. The efficacy of the proposed approach is demonstrated by an early and accurate detection of terminal voltage collapse over a set of discharge tests conducted using multiple batteries.

Abstracts:The need for the high-speed analogue-to-digital converters demands the use of regenerative comparators. The strong positive feedback present in the regenerative comparators helps the comparator to work efficiently at the high-speed operations. This work proposes a low power auxiliary circuit to improve the high-frequency performance of the comparator. The proposed architecture along with the conventional comparators is simulated in 65-nm complementary metal oxide semiconductor (CMOS) technology with a supply voltage of 0.9 V. The maximum operating frequency of the proposed comparator is 6.25 GHz for a differential input voltage of 1 mV.

Abstracts:In this paper, the authors propose the use of electrostatic doping for <i>n</i>⁺ drain region formation in Junctionless accumulation mode field effect transistors (JAMFET). This electrostatically doped drain (EDD) JAMFET employs an additional unbiased electrode (auxiliary electrode) of low workfunction on the intrinsic drain region. This technique effectively suppresses the tunneling leakage, thereby reducing <i>I</i>_OFF by 6 orders. The tunneling of electrons from valence band of channel to conduction band of drain happens due to enhanced band bending in OFF-state (<i>V</i>_GS = 0 V, <i>V</i>_DS = 1 V). The presence of additional electrode in EDD-JAMFET increases the width of tunnel barrier formed at channel-drain junction in OFF-state improving the <i>I</i>_ON/<i>I</i>_OFF ratio by 6 orders. The gate length scaling demonstrates that leakage suppression of EDD-JAMFET is more effective with approximately 3 orders smaller <i>I</i>_OFF even at gate length of 5 nm. The performance of graded channel device (GC-EDD-JAMFET) by electrostatic doping is also explored. Significant improvements are observed in terms of <i>I</i>_ON/<i>I</i>_OFF, subthreshold slope SS, DIBL and <i>f</i>_T. Finally, the analogue parameters such as Transconductance generation factor <i>G</i>_m/<i>I</i>_D, Intrinsic gain <i>A</i>_V, output conductance <i>G</i>_D, and `<i>G</i>_m/<i>I</i>_D &#x00D7; <i>f</i>_T' performance metrics are investigated which show significant improvement at small bias current, making it suitable for ultra-low power applications.

Abstracts:This study presents an adaptive analogue calibration method to compensate electrode-skin impedance mismatch during biopotential signal (electrocardiogram, electroencephalogram and electromyogram) acquisition with enhanced immunity to electromagnetic interference (EMI). The method continuously measures the variation of the impedance mismatch between the electrode-skin interfaces arising primarily due to motion artefacts, and thereafter compensate for the resulting distortions at the output. The compensation is done with the help a proportional-integral-derivative controller in the feedback loop, together with the acquisition of the biopotential signals. A common mode shunt feedback at the output attenuates the common mode EMI and reduces the common mode deviation. As compared to previously reported techniques, the proposed technique refutes any need for offline manual calibration and shows a significant improvement in EMI attenuation without interrupting the main system's operation. This study explains the proposed technique with the comprising blocks, illustrates the theoretical models and analyses, and evaluates the superior performances of the proposed method by comparing the responses with those obtained from the other EMI-Immune electrode mismatch compensating front-ends existing in the literature.

Abstracts:This study presents a complementary metal-oxide-semiconductor (CMOS) 140 GHz on-off-keying (OOK) modulator with high isolation and low ON-state insertion loss based on a cascaded architecture of a switch-based and amplifier-based modulators. A prototype implemented in a 65 nm bulk CMOS process operates at 140 GHz carrier input and realises 24.6 dB isolation, whereas in ON-state it achieves 0.3 dB gain and -0.2 dBm OP1 dB with 8 mW power consumption. Up to 11 Gb/s modulation is verified with the spectrum and demodulated waveform measurements. The proposed OOK modulator occupies the core area of 250&#x00D7;380 &#x03BC;m².