Abstracts:Uncertainties in nonlinear systems can significantly hinder the effectiveness of traditional filtering methods, leading to suboptimal state estimation and compromising overall performance and robustness. Therefore, an extended H $_{\infty }$ filtering based on reproducing kernel Hilbert space (RKHS) is proposed for addressing the state estimation issue existing in the nonlinear system with uncertainty in this brief. In particular, this extended H $_{\infty }$ filtering is derived in RKHS by using conditional embedding operator and a robust optimization framework. In addition, it employs an adaptive kernel size method to enhance the model’s generalization capability. Moreover, an online sampling method based on Nyström approach is utilized to reduce computational complexity. Simulation results in chaotic time series prediction and SOC estimation demonstrate that the proposed algorithm outperforms the other competitive algorithms.

Abstracts:This brief presents a novel approach to extend the zero voltage switching (ZVS) range in the current-fed parallel resonant converter for wireless power transfer in an automated guided vehicle (AGV). Unlike previous methods that focus on tuning capacitors or inductors, the proposed method is to resonate the matching capacitor with a lumped inductor to enable ZVS in the region where the ZVS condition is not met, which is an LC resonance approach. The power dissipation due to ZVS failure is analyzed, and the proposed method to guarantee ZVS operation is described in detail. The simulated and measured results verified that the proposed method extends the range of ZVS by approximately 242% and achieves an efficiency improvement of up to 10.69% under the same load conditions compared to the conventional method.

Abstracts:This brief presents a low-power redundant transition- and contention-free flip-flop with fewer clock transistors. Called reduced clock-load flip-flop (RCLFF), the proposed flip-flop minimizes the clock load by merging clock transistors to reduce the clock power consumption regardless of input switching activity. It also provides completely redundant transition-free operation, further reducing the power consumption. Reliable operation with no floating node and contention can enable further power saving by letting the flip-flop in the near-threshold voltage (NTV) region. Performance evaluation in a 28-nm CMOS process indicates that RCLFF achieves up to 60.9% power reduction compared to conventional flip-flops at 0.1 switching activity. By reducing power consumption with moderate DQ latency, the power-delay product (PDP) of RCLFF is improved by up to 64.5%. The Monte-Carlo simulation result reveals that RCLFF can operate reliably down to a 0.3 V supply voltage regardless of process, voltage, and temperature (PVT) variations.

Abstracts:In order to enhance the position estimation accuracy of sensorless control of permanent magnet synchronous motor (PMSM), this brief proposes an improved super-twisting observer (STO) combined with a novel position compensation phase-locked loop (PLL) scheme. In this sensorless technology, the improved STO is designed using linear and nonlinear correction terms to achieve precise reconstruction of back electrimotive force (EMF) and finite-time convergence. With the back-EMF accurately estimated, the position compensation PLL is presented to alleviate the position error introduced by the speed acceleration and deceleration ramps when extracting position and speed information. Ultimately, the experimental comparisons on a 0.75-kW PMSM drive reveal that the proposed sensorless scheme has superior position estimation accuracy in both speed dynamics and steady state compared with the conventional schemes.

Abstracts:This brief presents a development of a real-time hardware-in-the-loop system using software-defined radios to emulate multi-sensor networked control systems (NCS) under real-world conditions. Also, a dedicated estimation algorithm for NCS using binary phase shift keying modulation, addressing signal-to-noise ratio constraints and channel characteristics from a sensor fusion perspective is addressed. This system supports remote placement of modules like sensors, estimators, and controllers interconnected via wireless channels, enabling distributed operation. This brief experimentally evaluates two scenarios: one involving a single measurement and the other utilizing a fusion-based approach. The proposed system, acting as a testbed helps in system evaluation before deployment.

Abstracts:A wideband, compact, digitally-assisted variable gain phase shifter (VGPS) in a 65-nm CMOS process is presented for Ka-band applications. A digitally-assisted variable gain amplifier (VGA) architecture with a wide gain-control dynamic range and minimal input/output impedance variations is proposed by combining bias and digital control. Using only a one-stage digitally-assisted VGA, the VGPS achieves orthogonal phase and gain control with low RMS gain and phase errors in a compact size. Theoretical analysis is explored to provide physical insight into the working mechanism of the VGPS. In this design, the proposed VGPS leverages 3 bits for 18-dB gain tuning and 4 bits for 360° phase control. Measurements show that the VGPS exhibits an average peak gain of 0.6 dB at 28.4 GHz with a 3-dB bandwidth from 25.4 to 35.6 GHz. The measured RMS gain and phase errors is below 0.37 dB and 3°, respectively, from 25.4 to 34 GHz. It is implemented in a 65-nm CMOS process with the core area of $0.19~{\mathrm { mm}}^{2}$ excluding the pads.

Abstracts:An inductor-less wideband LNA is designed for a 5G midband applications. The noise reduction technique is proposed to address the trade-off between input return loss $(S_{11})$ and noise figure (NF). The proposed structure combines self-cascode transistors and composite transistors to increase $g_{m}$ without consuming additional current, which can improve NF and linearity. In contrast to conventional noise cancellation techniques, the proposed technique improves the NF by reusing current without a path for noise cancellation. The proposed LNA is designed with a 0.13- $\mu $ m CMOS process and measured. In experiments, the proposed LNA shows a power gain $(S_{21})$ of 21.5 dB over a 3dB bandwidth of $0.01\sim 1$ .7 GHz, and $S_{11}$ is less than −10 dB over the range 0.01~2 GHz. Also minimum NF of proposed LNA is 1.1 dB. In case of the linearity, the proposed LNA shows an input-referred third-order intercept point (IIP3) of −7.5 - 2.3 dBm. The power consumption is 9.1 mW from a 1.3 V supply voltage and chip area is 0.18 mm2.

Abstracts:This brief introduces a digital calibration technique to boost the input impedance of instrumentation amplifiers (IAs) with digitally tunable input impedance. The technique employs two machine learning-driven optimization algorithms, the genetic algorithm (GA) and the particle swarm optimization (PSO) algorithm, to efficiently control integrated capacitor banks within the IA for the determination of the optimal input impedance. These algorithms offer a significant time reduction compared to a calibration with an exhaustive search, reducing calibration time by a factor of over $10^{6}$ (with four 9-bit digital control words) while conserving computational resources. A prototype platform was developed to automatically optimize a fabricated IA test chip designed with 65-nm CMOS technology, which allows to test the machine learning algorithms using a microcontroller to control the digitally tunable input impedance. With an extra input capacitance of 100 pF, the GA algorithm achieved an input impedance of 1.75 G $\Omega $ after four generations (iterations), while the PSO algorithm achieved 1.27 G $\Omega $ with five iterations.

Abstracts:This brief presents a series-LC-assisted oscillator. By utilizing the series LC, the tank impedance at the oscillation frequency is significantly reduced compared to the conventional parallel LC tank, which contributes to reducing the phase noise (PN). Additionally, large-size cross-coupled transistors should be utilized to maintain the oscillation due to the low tank impedance. This induces a large parasitic capacitance that limits the frequency tuning range (FTR) at high frequencies in the conventional cross-coupled oscillator. In contrast, the presented oscillator can operate above 10 GHz with a sufficient FTR, thanks to the capacitance-boosting capability of the series LC. Fabricated in a 65 nm CMOS process, the oscillator achieves a PN of −140.2 dBc/Hz at 10 MHz offset from a 10.7 GHz carrier, consuming a power consumption of 21 mW, resulting in a figure of merit (FoM) of 187.5 dBc/Hz.

Abstracts:A dynamic comparator reset scheme based on the flying capacitor is proposed. The reset power used to charge the integration nodes of the comparator is nearly halved by exploiting the existent integration capacitors with only a single D-flip-flop and few switches. The proposed reset scheme improves the energy efficiency while the small CLK-OUT delay of the dynamic comparator is maintained. The prototype comparators with the conventional or the proposed reset scheme are fabricated in a 22-nm bulk CMOS process. The measurement results of the delay, input-referred noise, and energy consumption show that the flying-capacitor-based reset scheme boosts the overall performance of both the conventional StrongARM and Elzakker’s comparator by about 1.8-times.