Welcome to the IKCEST

IEEE Design & Test | Vol.35, Issue.6 | | Pages 78-85

IEEE Design & Test

GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits

M. Amin SabetBehnam GhavamiMohsen Raji  
Abstract

In this article, a team of researchers from Shiraz University and the Shahid Bahonar University of Kerman, Iran, investigates soft error rate (SER) estimation. They propose an analytical framework to estimate SER accurately and an implementation on graphic processing units (GPUs) that is able to scale to circuits composed of thousands of gates. The framework exploits several levels of parallelism in the SER estimation process to map it efficiently onto GPUs.

Original Text (This is the original text for your reference.)

GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits

In this article, a team of researchers from Shiraz University and the Shahid Bahonar University of Kerman, Iran, investigates soft error rate (SER) estimation. They propose an analytical framework to estimate SER accurately and an implementation on graphic processing units (GPUs) that is able to scale to circuits composed of thousands of gates. The framework exploits several levels of parallelism in the SER estimation process to map it efficiently onto GPUs.

+More

Cite this article
APA

APA

MLA

Chicago

M. Amin SabetBehnam GhavamiMohsen Raji,.GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits. 35 (6),78-85.

Disclaimer: The translated content is provided by third-party translation service providers, and IKCEST shall not assume any responsibility for the accuracy and legality of the content.
Translate engine
Article's language
English
中文
Pусск
Français
Español
العربية
Português
Kikongo
Dutch
kiswahili
هَوُسَ
IsiZulu
Action
Recommended articles

Report

Select your report category*



Reason*



By pressing send, your feedback will be used to improve IKCEST. Your privacy will be protected.

Submit
Cancel