In this paper, we propose the use of a p⁺ core in the core-shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio (I_ON/I_OFF) in n-NW junctionless FETs (NWJLFETs). We show that the lateral bandto-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p⁺ core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio (I_ON/I_OFF) of ~10⁷ even for a channel length of 7 nm.

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volume depletion onstate to offstate current ratio isubonsubisuboffsub calibrated 3d simulations gate induced drain leakage psupsup core lateral bandtoband tunneling induced parasitic bipolar junction transistor action coreshell nanowire cs nw architecture tunneling width source to channel barrier height nnw junctionless fets csjlfet

Shubham Sahay, Mamidala Jagadesh Kumar,.Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture. 63 (9),3790-3794.

Shubham Sahay, Mamidala Jagadesh Kumar,"Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture" 63

Shubham Sahay, Mamidala Jagadesh Kumar,"Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture"