Fladiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

+More

silicon charge collection effects soft errors sers vlsi sequential logic memories soft error rate ser powerperformancearea highintensity neutron technology single event upsets seus radiation particle

Patel, J,Karnik, T ,Hazucha, P ,.Characterization of soft errors caused by single event upsets in CMOS processes. 1 (),16.

Patel, J,Karnik, T ,Hazucha, P ,"Characterization of soft errors caused by single event upsets in CMOS processes" 1

Patel, J,Karnik, T ,Hazucha, P ,"Characterization of soft errors caused by single event upsets in CMOS processes"